Support for RISC-V ISA in Sting

RISC-V is an open-source instruction set architecture (ISA) based on reduced instruction set computing (RISC) fundamentals. It has been designed to support extensive customization and specialization across multiple classes of processors. Looking at the growing interest for RISC-V in industry, we have ported the software stack of Sting to support functional verification of CPU/SoC implementations based on RISC-V ISA. A report on Sting's beta-release for RISC-V can be found here.

Sting Trial Version to be Available Soon

Our team is working on release of a trial version which can be used to generate functional stimulus using the test development mechanisms of Sting. The idea behind this is to enable future users with a hands-on platform to create tests and evaluate the software on their target platforms before licensing the full version. A subset of Sting's functionalities will be provided for a fixed time duration under a license. Feel free to contact us in case you would want to evaluate the demo version of Sting.

Coverage Data from Sting Tests on Qualcomm Dragonboard 410C

Our previous newsletter had a note on enabling Sting on Qualcomm Dragonboard 410C board. As an exercise to evaluate the quality of test stimulus generated by Sting, we collected coverage data on some of the performance monitoring events supported on the board. Same set of events were profiled for few open source benchmarks and the data was compared with results from the Sting tests. The entire activity is recorded in this blog with a comparison of coverage data for few of the performance monitoring events.

Latest Additions to Sting's Test Stimulus Library

A number of test configurations and standalone test applications have been added to the library of functional test stimulus in Sting. Tests for memory ordering, virtual memory system architecture, cache coherency scenarios, coverage of FP/SIMD instructions and concurrent execution of CPU and IO traffic, are among the several additions that have been made so far.

Upcoming Features in Sting

We are working on plenty of exciting things to enhance Sting's capabilities while addressing the issues with functional verification of complex system-on-chips. Some of the features which will be released soon are - (1) Framework to auto-generate test configurations which scale according to the SoC/hardware configuration it is going to run on, (2) Programming mechanism to characterize different software and hardware configurations/SKUs of a SoC for a particular test stimulus, (3) Easy and flexible programming constructs to create any sequence of register and memory access

Valtrix Systems featured on Semiconductor Engineering

Valtrix Systems got featured on Semiconductor Engineering recently. The article talks about Sting's approach and methodology towards functional verification of SoC/CPU implementations and highlights some of the benefits that SoC/IP developers will get on using Sting in every stage of design and validation. Here is the link to the article.